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PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
SC1172/3
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1172/3 combines a synchronous voltage mode controller with a low-dropout linear regulator providing most of the circuitry necessary to implement two DC/DC converters for powering advanced microprocessors such (R) as Pentium II (Klamath) or Deschutes. The SC1172/3 switching section features an integrated 5 bit D/A converter, pulse by pulse current limiting, integrated power good signaling, and logic compatible shutdown. The SC1172/3 switching section operates at a fixed frequency of 200kHz, providing an optimum compromise between size, efficiency and cost in the intended application areas. The integrated D/A converter provides programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.30V to 2.05V in 50mV increments with no external components. The SC1172/3 linear section is a high performance positive voltage regulator design for either the GTL bus supply at 1.5V (SC1172) or an adjustable output (SC1173). The output of the linear regulator can provide up to 5A or more with the appropriate external MOSFET.
FEATURES * Synchronous design, enables no heatsink solution * 95% efficiency (switching section) * 5 bit DAC for output programmability * On chip power good function * Designed for Intel Pentium(R) II VRM8.1 require*
ments 1.5V or Adj. @ 1% for linear section
APPLICATIONS * Pentium(R) ll or Deschutes microprocessor supplies * Flexible motherboards * 1.3V to 3.5V microprocessor supplies * Programmable dual power supplies ORDERING INFORMATION
Part Number
(1)
Package
Linear Voltage
Temp. Range (TJ)
SC1172CSW SC1173CSW
SO-24 SO-24
1.5V Adj.
0 to 125C 0 to 125C
Note: (1) Add suffix `TR' for tape and reel.
PIN CONFIGURATION
BLOCK DIAGRAM
VCC CS- CS+ EN BSTH 1.25 REF VCC 70mV VID4 VID3 VID2 VID1 VID0 D/A & SHUTDOWN LOGIC CURRENT LIMIT LEVEL SHIFT AND HIGH SIDE MOSFET DRIVE R OSCILLATOR S Q PGNDH
Top View
AGND NC NC LDOS VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL
VOSENSE OPEN COLLECTORS PWRGOOD VCC
DH
SHOOTTHRU CONTROL ERROR AMP SYNCHRONOUS MOSFET DRIVER BSTL
DL
OVP
(24 Pin SOIC)
PGNDL AGND 1.25V REF FET CONTROLLER
LDOV
GATE
LDOS
Pentium is a registered trademark of Intel Corporation
1
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
SC1172/3
ABSOLUTE MAXIMUM RATINGS
Parameter VCC to GND PGND to GND BST to GND Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 seconds Thermal Impedance Junction to Ambient Thermal Impedance Junction to Case TA TJ TSTG TL JA JC Symbol VIN Maximum -0.3 to +7 1 -0.3 to +15 0 to +70 0 to +125 -65 to +150 300 80 25 Units V V V C C C C C/W C/W
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CSp-CSm) < 60mV; LDOV = 11.4V to 12.6V; TA = 25oC
PARAMETER Switching Section Output Voltage Supply Voltage Supply Current Load Regulation Line Regulation Minimum operating voltage Current Limit Voltage Oscillator Frequency Oscillator Max Duty Cycle DH Sink/Source Current DL Sink/Source Current Output Voltage Tempco Gain (AOL) OVP threshold voltage OVP source current Power good threshold voltage Dead time Linear Section Quiescent current Output Voltage (SC1172) Reference Voltage (SC1173) Feedback Pin Bias Current (SC1173) Gain (AOL) Load Regulation Line Regulation Output Impedance Notes: (1) See Output Voltage table (2) In application circuit (c) 1999 SEMTECH CORP.
CONDITIONS IO = 2A VCC VCC = 5.0 IO = 0.8A to 15A
MIN
TYP
MAX
UNITS
See Note 1. 4.2 8 1 0.5 60 180 90 1 1 70 200 95 7 15 V mA % % V mV kHz % A A o ppm/ C dB % mA % ns mA V V uA dB % %
4.2 80 220
BSTH-DH = 4.5V, DH-PGNDH = 2V BSTL-DL = 4.5V, DL-PGNDL = 2V
VOSENSE to VO VOVP = 3.0V 10 88 50
30 35 120
100
112 100
LDOV = 12V
LDOS to GATE (2) IO = 0 to 8A
5 1.485 1.500 1.515 1.252 1.265 1.278 10 90 0.3 0.3 200
2 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
SC1172/3
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name AGND NC NC LDOS VCC OVP (1) PWRGOOD CSCS+ PGNDH DH PGNDL DL BSTL BSTH (1) EN VOSENSE (1) VID4 (1) VID3 (1) VID2 (1) VID1 (1) VID0 LDOV GATE Pin Function Small Signal Analog and Digital Ground No connection No Connection Sense Input for LDO Input Voltage High Signal out if VO>setpoint +20% Open collector logic output, high if VO within 10% of setpoint Current Sense Input (negative) Current Sense Input (positive) Power Ground for High Side Switch High Side Driver Output Power Ground for Low Side Switch Low Side Driver Output Supply for Low Side Driver Supply for High Side Driver Logic low shuts down the converter; High or open for normal operation. Top end of internal feedback chain Programming Input (MSB) Programming Input Programming Input Programming Input Programming Input (LSB) +12V for LDO section Gate Drive Output LDO
Top View
AGND NC NC LDOS VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL
(24 Pin SOIC)
Note: (1) All logic level inputs and outputs are open collector TTL compatible.
3 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
SC1172/3
OUTPUT VOLTAGE
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CSp-CSm) < 60mV; TA = 25oC
PARAMETER Output Voltage
CONDITIONS IO = 2A in Application Circuit
VID 43210 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000
MIN 1.287 1.336 1.386 1.435 1.485 1.534 1.584 1.633 1.683 1.732 1.782 1.831 1.881 1.930 1.980 2.029 1.980 2.079 2.178 2.277 2.376 2.475 2.574 2.673 2.772 2.871 2.970 3.069 3.168 3.267 3.366 3.465
TYP 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 2.050 2.000 2.100 2.200 2.300 2.400 2.500 2.600 2.700 2.800 2.900 3.000 3.100 3.200 3.300 3.400 3.500
MAX 1.313 1.364 1.414 1.465 1.515 1.566 1.616 1.667 1.717 1.768 1.818 1.869 1.919 1.970 2.020 2.071 2.020 2.121 2.222 2.323 2.424 2.525 2.626 2.727 2.828 2.929 3.030 3.131 3.232 3.333 3.434 3.535
UNITS V
4 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
12V
October 25, 1999
5V
+
R1 10 0.1uF U1 5 VCC OVP VID0 VO SENSE PWRGOOD VID4 4uH 15 11 10 13 14 23 R13 * 4 C8 1500uF C9 1500uF Q2 BUK556 BSTH DH PGNDH DL BSTL LDOV LDOS R12 * Q3 BUK556 18 7 L1 R5 5mOhm C6 1500uF VID1 VID2 VID3 EN AGND PGNDL GATE NC NC SC1172/3CS 17 C7 1500uF CS8 Q1 BUK556 CS+ 6 22 21 20 19 16 1 12 24 2 3 9 10k C4 1.00k 2.32k R16 R3 R4
(c) 1999 SEMTECH CORP.
C1 0.1uF
+
APPLICATION CIRCUIT
C2 1500uF
C3 1500uF
VCC_CORE
EN
+ + +
+
C10 0.1uF
OVP
C5
VID0
0.1uF
VID1
VID2
VID3
VID4
VLIN
PWRGD
+ +
C21 330uF C11 330uF
+
C12 330uF
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
VINLIN (NORMALLY 3.3V)
R17 ** 100k
NOTE:
FOR SC1172, R12 AND R13 ARE NOT REQUIRED. CONNECT LDOS (PIN4) DIRECTLY TO VLIN TO GENERATE 1.5V TO OUTPUT. * SEE "SETTING LDO OUTPUT VOLTAGE" TABLE. ** R17 REQUIRED IF VINLIN CAN BE PRESENT WITHOUT 12V BEING PRESENT.
SC1172/3
5
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
SC1172/3
MATERIALS LIST
Qty. Reference 4 6 3 1 3 1 1 1 1 1 1 1 1 Part/Description Vendor Various SANYO Various 8 Turns 16AWG on MICROMETALS T50-52D core See notes IRC Various Various Various Various Various Various SEMTECH See Table (Not required for SC1172) See Table (Not required for SC1172) FET selection requires trade-off between efficiency and cost. Absolute maximum RDS(ON) = 22 m for Q1,Q2 OAR-1 Series MV-GX or equiv. Low ESR Notes
C1,C5,C13,C 0.1F Ceramic 18 C2,C3,C14C17 C11,C12, C21 L1 Q1,Q2,Q3 R4 R5 R6 R1 R12 R13 R17 U1 1500F/6.3V 330F/6.3V 4H See notes 5m 2.32k, 1%, 1/8W 1k, 1%, 1/8W 10, 5%, 1/8W 1%, 1/8W 1%, 1/8W 100K, 5% 1/8W SC1172/3CSW
SETTING LDO OUTPUT VOLTAGE
RB VO LDO 3.45V 3.30V 3.10V 2.90V 2.80V 2.50V 1.50V R12 105 105 102 100 100 100 100 RA R13 182 169 147 130 121 97.6 18.7
VOUT =
1.265 (R A + R B ) + (IFB R A ) RB
Where : IFB = Feedback pin bias current R A = Top feedback resistor R B = Bottom feedback resistor See layout diagram for clarification R A and R B must be low enough so that the (IFB R A ) term does not cause significant error
6 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
95% 95%
SC1172/3
90%
90%
Efficiency
Efficiency
85%
85%
80% 3.5V Std 3.5V Sync 3.5V Sync Lo Rds
80% 2.8V Std 2.8V Sync 2.8V Sync Lo Rds
75%
75%
70% 0 2 4 6 8 Io (Amps) 10 12 14 16
70% 0 2 4 6 8 Io (Amps) 10 12 14 16
Typical Efficiency at Vo=3.5V
95%
Typical Efficiency at Vo=2.8V
95%
90%
90%
Efficiency
Efficiency
85%
85%
80% 2.5V Std 2.5V Sync 2.5V Sync Lo Rds
80% 2.0V Std 2.0V Sync 2.0V Sync Lo Rds
75%
75%
70% 0 2 4 6 8 Io (Amps) 10 12 14 16
70% 0 2 4 6 8 Io (Amps) 10 12 14 16
Typical Efficiency at Vo=2.5V
Typical Efficiency at Vo=2.0V
Typical Ripple, Vo=2.8V, Io=10A
Transient Response Vo=2.8V, Io=300mA to 10A
7 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
SC1172/3
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary for successful implementation of the SC1172/3 PWM controller. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept
12V IN
as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency.
5V
10 1 2 3 4 0.1uF 5 6 0.1uF 7 8 9 10 11 12
AGND NC NC LDOS VCC OVP PWRGOOD CSCS+ PGNDH DH PGNDL GATE LDOV VID0 VID1 VID2 VID3 VID4 VO SENSE EN BSTH BSTL DL
24 23 22 Cin 21 20 19 18 17 16 15 14 13 Q2 Cout 4uH + Q1 + 1.00k 5mOhm Vout 2.32k
SC1172/3
RA
Heavy lines indicate
5V Q3 + Cin Lin RB Cout Lin + Vo Lin
high current paths.
For SC1172, RA and RB are not required. LDOS connects to Vo Lin
Layout diagram for the SC1172/3
8 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1172/3 is best placed over a quite ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. PGNDH and PGNDL should be returned to the ground plane close to the package. The AGND pin should be connected to the ground side of (one of) the output capacitor(s). If this is not possible, the AGND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 6) Vcc for the SC1172/3 should be supplied from the
SC1172/3
5V supply through a 10 resistor, the Vcc pin should be decoupled directly to AGND by a 0.1F ceramic capacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces running back to CS+ and CS- on the SC1172/3 should run parallel and close to each other. The 0.1F capacitor should be mounted as close to the CS+ and CS- pins as possible. 8) Ideally, the ground for the LDO section should be returned to the ground side of (one of) the switching section output capacitor(s).
5V
+
Vout +
Currents in various parts of the power section
9 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
SC1172/3
COMPONENT SELECTION
SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from:
fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
R ESR
V t It
ILRIPPLE=
VIN 4L fOSC
Where Vt = Maximum transient voltage excursion It = Transient current step
For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10m. To meet this kind of ESR level, there are three available capacitor technologies:
Each Capacitor Technology Low ESR Tantalum OS-CON Low ESR Aluminum C (F) 330 330 1500 ESR (m) 60 25 44 Qty. Rqd. 6 3 5 Total C (F) 2000 990 7500 ESR (m) 10 8.3 8.8
Ripple current allowance will define the minimum permitted inductor value. POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as:
2 PCOND = IO RDS(on)
where = duty cycle VO VIN
b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then:
PSW = IO VIN 10 -2
The choice of which to use is simply a cost /performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from:
or more generally,
PSW =
IO VIN (t r + t f ) fOSC 4
L
R ESR C (VIN - VO ) It
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be:
PRR = Q RR VIN fOSC
To a first order approximation, it is convenient to only consider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be:
The calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp
10 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999 FET type RDS(on) (m) PD (W) 2.48 0.79 1.53 Package TO220 D PAK SO-8
2
SC1172/3
BUK556H 22 IRL2203 Si4410 7.0 13.5
BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by:
2 PCOND = IO RDS( on ) (1 - )
INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size.
For the example above: FET type RDS(on) (m) PD (W) 1.95 0.62 1.20 7.0 13.5 Package TO220 D PAK SO-8
2
BUK556H 22 IRL2203 Si4410
Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed o circuit board material, thermal impedances of 40 C/W 2 o for the D PAK and 80 C/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below: Temperature rise ( C) FET type Top FET
(1) o
Bottom FET 39.0 24.8 96
(1)
BUK556H 49.6 IRL2203 Si4410
o
31.6 122.4
(1) With 20 C/W Heatsink It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4.
11 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER WITH LOW DROPOUT REGULATOR CONTROLLER
October 25, 1999
SC1172/3
OUTLINE DRAWING
JEDEC MS-013AD B17104B
ECN99-667
12 (c) 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

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